Thermal conductivity reduction in phononic nanomesh structures

Device Fabrication All devices were prepared on silicon-on-insulator (SOI; Soitec Inc.) wafers. The SOI wafers were pre-doped by thermally diffusing spin-on-dopant (Boron A; Filmtronics, Inc.) with rapid thermal annealing (RTA) at 820C for 3 minutes. The resulting sheet resistance indicates a doping concentration of 2x10 cm, with the thickness of the silicon epilayer determined by atomic force microscopy to be 25 nm, 22 nm and 20 nm (depending on the device) with a variance of 1 nm. The nanomesh films (NM) and nanowires (NWA) are fabricated by the SNAP technique [30], while the e-beam nanomesh (EBM) and thin films (TF) are defined by e-beam lithography (EBL). For the NM devices, two perpendicularly aligned Pt nanowire arrays are made using two consecutive superlattice nanowire pattern array (SNAP) procedures on top of an SOI wafer (Soitec, Inc.). SNAP protocols are described in Refs. 17 and 30. For the NWA devices only one SNAP procedure is carried out, resulting in a single, aligned Pt nanowire array. For the EBM and TF devices, e-beam lithography and metallization are used to make the transfer-ready Pt nanostructures. Next, we define the membranes